The MOS capacitor disclosed in Patent Document 1 comprises a first MOS transistor having source terminal and drain terminal commonly, and a second MOS transistor similarly having source terminal and drain terminal commonly, and the first MOS transistor and the second MOS transistor are unified in p-channel type or n-channel type, and individual gate terminals and source-drain terminals are connected in cross multiplication.
In Patent Document 1, depletion mode MOS transistors are used as first and second MOS transistors T1, T2. Capacity curves of the first and the second MOS transistors T1, T2 are mutually interpolating opposite shapes, and a nearly flat capacity change curve is obtained when the both are added.
It is also said that a similar characteristic is obtained when enhancement mode MOS transistors are used as first and second MOS transistors.
Patent Document 1: Japanese Unexamined Patent Application Publication No. H5 (1993)-82741